The present invention relates to a microcomputer having direct memory access control means incorporated therein, peripheral devices electrically connected to the microcomputer, and a data processing system using the microcomputer. The present invention also relates to a technique which is effective for use in a computer system intended to provide multitask-based high-speed operations.
There has recently been a demand for improvements in data throughput in a microcomputer. If the quantity of processed data to be loaded on a CPU (Central Processing Unit) increases, it is difficult to improve the data throughput of the microcomputer. Therefore, an attempt has been made to incorporate a peripheral module for performing data transfer control into a microcomputer in place of the CPU to thereby distribute the burden of data processing on the CPU. As such a peripheral module, a DMAC (Direct Memory Access Controller), for example, is known.
In the conventional microcomputer having a DMAC incorporated therein, the CPU is given the task of initially setting control information (such as transfer addresses, the number of transfers, transfer modes, transfer directions, etc.) necessary for data transfer into the DMAC.
As an example of such a direct memory access controller reference is made to a publication entitled xe2x80x9cConfiguration and Design of Computer (Last Volume)xe2x80x9d published by Nikkei BP corporation, pp. 520-521, Apr. 19, 1996.
However, according to an investigation carried out by the present inventors, there are cases in which an excessive time is required to initially set the data transfer control information into the DMAC using the CPU, depending on the state of data processing by the CPU or the state of utilization of an external data bus. It has been proven that, in such a consequence, excessive time has been taken for data transfer processing. Therefore, there may be cases in which data transfer cannot be started and ended with the timing required by a data transfer request source. There is also a possibility that, since the CPU is used to set the data transfer control information, the CPU cannot be distributed to other processes during that time, so that the microcomputer will exhibit a reduced data processing performance. This becomes one factor which will reduce the performance of the entire system.
An object of this invention is to provide a microcomputer and a data processing system which are capable of setting data transfer control information without placing a burden on the CPU, thereby to carry out a direct memory access with increased system performance.
Another object of this invention is to provide a microcomputer and a data processing system which are capable of immediately responding to a request made from a data transfer request source to start data transfer based on a direct memory access.
A further object of this invention is to provide a peripheral device which is suitable for the issuance of a data transfer request.
The above and other objects and novel features of the present invention will become more apparent from the description provided in the present specification and from the accompanying drawings.
Typical features of the present invention as disclosed in the present application will be briefly described as follows.
That is, when data transfer is carried out, an input/output device (65), used as a transfer request source, outputs a data transfer set command (DTR) for specifying a data transfer channel, a data transfer address, the number of data transfers, a data transfer mode, a data transfer direction, etc. to a bus (60) together with a data transfer request (TR) without involving the CPU (3). According to the data transfer set command, data transfer control information is set into the direct memory access control means (8, 100) and hence data transfer placed under direct memory access control is started between the input/output device used as the data transfer request source and a memory specified by a transfer address. Thus, when the input/output device used as the data transfer request source desires to perform a data transfer, the input/output device can carry out data transfer processing at its own timing without regard to the state of processing of the microcomputer (1), whereby data transfer using the input/output device as a principal part or base can be carried out. Since the CPU is not required to effect the initial setting of the data transfer control information at this time, no load is imposed on the CPU, and the CPU can be distributed to other processes during that time, thereby contributing to an overall improvement in the data processing performance of the microcomputer and the data processing performance of the data processing system.
A data processing system comprises a microcomputer (1), a memory (600), an input/output device (65), and at least one bus (60, 61) commonly connected to the microcomputer, the memory and the input/output device. The microcomputer includes a central processing unit (3), direct memory access control means (8, 100) having a plurality of data transfer channels for performing data transfer control based on data transfer control information supplied from the central processing unit or the outside through the bus, and a bus state controller (5) for arbitrating competition between bus right requests supplied from the central processing unit, the direct memory access control means and the input/output device and for controlling a bus cycle for the bus. The input/output device acquires a bus right to send a data transfer request (TR) to the direct memory access control means and outputs a data transfer set command (DTR) for controlling the operation of the direct memory access control means to the bus, and the input/output device further performs the operation of inputting data to or outputting data from the bus in synchronism with a response (TDACK) corresponding thereto issued from the microcomputer, operating as a data transfer source for the control of the data transfer by the direct memory access control means. The direct memory access control means can execute a first operation (first normal data transfer operation) for performing data transfer control in accordance with the data transfer control information initially set by the data transfer set command.
In the first operation as described above, the input/output device, which makes a request for data transfer, can set data transfer control information and start data transfer control without involving the CPU. Here, the processing of the CPU ranges over various diverse operations. It has been considered that heretofore in the conventional microcomputer when the CPU is performing another processing at the time data transfer control information is to be set to the direct memory access control means, the processing of the CPU must be allowed to continue until the other process is ended or be interrupted by or through the issuing of an interruption or the like, so that an extended time is often required to set a data transfer control condition. It is estimated that since the timing for the start and end of data transfer is not taken, an influence will be exerted on the performance even upon the construction of a system. However, in accordance with this invention, owing to the direct setting of the data transfer control information by the input/output device without involving the CPU, as described above, the data transfer can be started regardless of the state of processing of the CPU, whereby the data transfer processing performance can be improved and the data transfer processing time can be shortened.
After the first operation, the direct memory access control means detects that the data transfer set command (DTR) supplied together with the data transfer request (TR) from the input/output device has been placed in a specific first state (MD1, MD0=xe2x80x9c0, 0xe2x80x9d), thereby making it possible to execute a second operation (first handshake protocol transfer operation) for performing data transfer control according to the initially set data transfer control information, using the same data transfer channel as that used for the first operation. A data transfer request at the time, in which it is unnecessary to change the initialization condition, can be simply made.
After the first operation or the second operation, the direct memory access control means is supplied with a data transfer request (TR) from the input/output device without the delivery of the data transfer set command, thereby making it possible to execute a third operation (second handshake protocol transfer operation) for performing data transfer control according to the initially set data transfer control information, using the same data transfer channel as that used for the immediately preceding data transfer operation. Since, in this case, the immediately preceding data transfer channel and the data transfer control information are used for data transfer, the input/output device can start the data transfer, even if it is not able to acquire a bus right to set such information.
Further, the direct memory access control means is supplied with the data transfer request (TR) from the input/output device with the data transfer set command (DTR) after the data transfer control information has been initialized by the CPU, thereby making it possible to execute a fourth operation (second normal data transfer operation) for performing data transfer control according to the data transfer control information initialized by the CPU, using a data transfer channel specified by the data transfer set command. The input/output device itself can start up the data transfer even by using the state of initialization by the CPU.
After the data transfer control information has been initially set by the CPU, the direct memory access control means is supplied with a data transfer request (TR) from the input/output device without the delivery of the data transfer set command, thereby making it possible to execute a fifth operation (third normal data transfer operation) for performing data transfer control according to the initially set data transfer control information, using the same data transfer channel as that used for the immediately preceding data transfer operation. Since the previously set data transfer control information is used in this case, the input/output device can start data transfer without acquiring a bus right.
The direct memory access control means detects that a data transfer set command supplied from the input/output device is placed in a specific second state (ID1, ID0=xe2x80x9c0, 0xe2x80x9d, MD1, MD0=xe2x80x9c0, 0xe2x80x9d and SZ2, SZ1, SZ0=xe2x80x9c1, 1, 1xe2x80x9d), thereby making it possible to force-complete a data transfer control operation. Thus, when data transfer is required, the input/output device can stop the data transfer operation of the already-activated direct memory access control means and request a data transfer with the highest priority.